// ram_sdport_w128d32.v

// Generated using ACDS version 19.1 670

`timescale 1 ps / 1 ps
module ram_sdport_w128d32 (
		input  wire [127:0] data,      //  ram_input.datain
		input  wire [4:0]   wraddress, //           .wraddress
		input  wire [4:0]   rdaddress, //           .rdaddress
		input  wire         wren,      //           .wren
		input  wire         clock,     //           .clock
		input  wire         rden,      //           .rden
		output wire [127:0] q          // ram_output.dataout
	);

	ram_sdport_w128d32_ram_2port_191_bmltdxy ram_2port_0 (
		.data      (data),      //  ram_input.datain
		.wraddress (wraddress), //           .wraddress
		.rdaddress (rdaddress), //           .rdaddress
		.wren      (wren),      //           .wren
		.clock     (clock),     //           .clock
		.rden      (rden),      //           .rden
		.q         (q)          // ram_output.dataout
	);

endmodule
